Pattern roughness significantly decreases yield and increases costs for semiconductor device geometries at and below the 10-nm node. To solve roughness issues the industry needs great analysis tools. But engineers haven't had an accurate and rigorous method for measuring and optimizing lithographic processes for roughness — until now.
Fractilia introduces MetroLER: the first software tool developed exclusively to enable semiconductor engineers to analyze scanning electron microscope (SEM) images for unbiased pattern roughness. Using patent pending technology, MetroLER provides device, tool, and resist manufacturers with the analysis tools they need to understand and solve a wide range of roughness issues, such as LER, LWR, and local CDU.